 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| revision history 1gb auto-a s4c64m16d2 - 84 ball fbga package revision details date rev 1.0 preliminary datasheet dec 2015 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C64M16D2-25BAN confidential - 1/59 - rev.1.0 dec 2015
features jedec standard compliant aec - q100 c ompliant jedec standard 1.8v i/o (sstl_18 - compatible) power supplies: v dd & v ddq = +1.8 v 0.1v automotive temperature: t c = -4 0 c ~105c supports jedec clock jitter specification f ully synchronous operation fast clock rate: 400 mhz differential clock, ck & ck # bidirectional single/di f ferential data strobe - dqs & dqs # 8 internal banks for concurrent operation 4- bit prefetch architecture internal pipeline architecture precharge & active power down programmable mode & extended mode registers posted cas # additive latency (al) : 0, 1, 2, 3, 4, 5 write latency = read latency - 1 t ck b urst lengths: 4 or 8 burst type: sequential / interleave dll enable/disable on - die termination (odt) rohs compli ant auto refresh and self refresh 8192 refresh cycles / 64ms - average refresh period 7.8 s @ -40 c Q t c Q + 85c 3.9 s @ +85c t c Q +1 05 c 84- ball 8 x 1 2. 5 x 1.2mm ( max) fbga p ackage - pb and halogen free table 1. ordering information part number org temperature maxclock (mhz) package AS4C64M16D2-25BAN 64mx16 automotive -40c to +105c 400 84-ball fbga table 2. speed grade information speed grade clock frequency cas latency trcd (ns) trp (ns) ddr2-800 400mhz 5 12.5 12.5 overview the 1gb ddr2 is a high -s peed cmos double -d ata- rate-t wo (ddr2), synchronous dynamic random - access memory (sdram) containing 102 4 mbits in a 16 -b it wide data i /o s . it is internally configured as a 8-b ank dram , 8 banks x 8m b addresses x 16 i/os . the device is designed to comply with ddr2 dram key features such as posted cas # with additive latency, wr ite latency = re ad latency -1 and on di e termination (odt) . all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cros s point of differential clocks (ck rising and ck# falling) all i/os are synchronized with a pair of bidirec tional s trobes (dqs and dqs#) in a source synchronous fashion. the addres s bus is used to c onvey row, column, and bank address information in ras #, cas# m ultiplexing s tyle. accesses beg in with the registration of a bank activate command, and then it is followed by a read or write command. read and write accesses to the ddr2 sdram are 4 or 8-bi t burst oriented; accesses start at a s elected location and continue for a programmed number of locations in a programmed sequence. operating the eight memory banks in an interleav ed fashion allows random access operation to occur at a higher rate than is possible with standard drams . an auto precharge function may be enabled to provide a self-t imed row precharge that is initiated at the end of the burst s equence. a sequential and gapless data rate is possible depending on burs t length, cas latency, and s peed grade of the dev ice. AS4C64M16D2-25BAN confidential - 2/59 - rev.1.0 dec 2015 figure 1. ball assignment (fbga top view) a b c d e 1 2 3 7 8 9 vdd nc dq14 vssq vddq dq9 dq12 vssq vdd nc vss udm vddq dq11 vss . vssq udqs# udqs vssq vddq dq8 dq10 vssq vssq ldqs# vddq dq15 vddq dq13 vddq f dq6 vssq ldm ldqs vssq dq7 g vddq dq1 vddq vddq dq0 vddq h dq4 vssq dq3 dq2 vssq dq5 j vddl vref vss vssdl ck vdd k cke we# ras# ck# odt l ba2 ba0 ba1 cas# cs# m a10 a1 a2 a0 vdd n vss a3 a5 a6 a4 p a7 a9 a11 a8 vss r vdd a12 nc nc nc AS4C64M16D2-25BAN confidential - 3/59 - rev.1.0 dec 2015 figure 2 . block diagram ck# cke cs# ras# cas# we# dll clock buffer command decoder column counter address buffer a10/ap a9 a11 a12 ba0 ba1 ba2 ck ldqs ldqs# udqs udqs# dq buffer ldm udm dq15 dq0 ~ odt ~ 8m x 16 cell array (bank #0) row decoder column decoder 8m x 16 cell array (bank #1) row decoder column decoder 8m x 16 cell array (bank #2) row decoder column decoder 8m x 16 cell array (bank #3) row decoder column decoder 8m x 16 cell array (bank #4) row decoder column decoder 8m x 16 cell array (bank #5) row decoder column decoder 8m x 16 cell array (bank #6) row decoder column decoder 8m x 16 cell array (bank #7) row decoder column decoder control signal generator a0 refresh counter data strobe buffer mode register AS4C64M16D2-25BAN confidential - 4/59 - rev.1.0 dec 2015 figure 3. state diagram (e)mrs setting mr, emr(1) emr(2) emr(3) ocd calibration initialization sequence idle all banks precharged self refreshing refreshing precharge power down activating active power down bank active writing writing with autoprecharge precharging reading with autoprecharge reading act ckel ckeh ckel wr rda rda wra wra wr rd rd pr, pra pr, pra pr, pra rda wra ckel ckeh ckel srf ckeh ref ckel wr rd pr ckel ckel automatic sequence command sequence ckel = cke low, enter power down ckeh = cke high, exit power down,exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) pr(a) = precharge (all) (e)mrs = (extended) mode register set srf = enter self refresh ref = refresh note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail. AS4C64M16D2-25BAN confidential - 5/59 - rev.1.0 dec 2015 ball descriptions table 3. ball descriptions symbol type description ck, ck # input differential clock: ck, ck # are driven by the system clock. all sdram input signals are sampled on the crossing of po sitive edge of ck and negative edge of ck#. output ( r ead) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input clock enable: cke activate s ( high) and deactivates (low ) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low . when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0-ba2 input bank address : ba0-ba2 define to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0 - a1 2 input address inputs : a0 - a1 2 are sampled during the bankactivate command (row address a0 - a1 2 ) and read/write command (column address a0 -a9 with a10 defining auto precharge ). cs # input chip select: cs # enables (sampled low) and disables (sampled high) the command decoder . all commands are masked when cs # is sampled high. cs # provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras # input row address strobe: the ras # signal defines the operation co mmands in conjunction with the cas # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . when ras # and cs # are asserted "low" and cas # is asserted "high," either the bankactivate command or the precha rge command is selected by the we # signal. when the we # is asserted "high," the bankactivate command is selected and the bank designated by b a is turned on to the active state. when the we # is asserted "low," the precharge command is selected and the bank designated by b a is switched to t he idle state after the precharge operation. cas # input column address strobe: the cas # signal defines the operation commands in conjunction with the ras # and we # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . whe n ras # is held "high" and cs # is asserted "low," the column access is started by asserting cas # "low." then, the read or write co mmand is selected by asserting we # high " or low ". we # input write enable: the we # signal defines the operation commands in conjunction with the ras # and cas # signals and is latched at the crossing of positive edges of ck and negative edge of ck# . the we # input is used to select the bankactivate or precharge command and read or write command. ldqs, ldqs # udqs udqs # input / ou tput bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. the data strobes ldos and udqs may be used in si ngle ended mode or paired with ldqs # and udqs # to provide differential pair signaling to the system during both reads and writes.a control bit at emr ( 1)[a10] enables or disables all complementary data strobe signals. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0 - dq7, udm masks dq8 - dq15. dq0 - dq15 input / output data i/o: the d ata bus input and output data are synchronized with positive and negative edges of dqs/dqs #. the i/os are byte - maskable during writes. odt input on die termination: odt enables internal termination resistance. it is applied to each dq, ldqs / ldqs # , udqs / udqs # , ldm, and udm signal. the odt pin is ignored if the emr ( 1) is programmed to disable odt. v dd s upply power supply: + 1.8 v 0.1v v ss supply ground AS4C64M16D2-25BAN confidential - 6/59 - rev.1.0 dec 2015 v ddl supply dll power supply: + 1.8 v 0.1v v ss dl supply dll ground v ddq supply dq power: + 1.8 v 0.1v . v ssq supply dq ground v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these p ins should be left unconnected. AS4C64M16D2-25BAN confidential - 7/59 - rev.1.0 dec 2015 operation mode table 4 shows the truth table for the operation commands. table 4. truth table (note (1), (2)) command state cke n-1 cke n dm ba 0-2 a 10 a 0- 9, 11 -12 cs # ras # cas # we # bankactivate idle (3) h h x v row address l l h h single bank precharge any h h x v l x l l h l all banks precharge any h h x x h x l l h l write active (3) h h x v l column address (a0 a9) l h l l write with autoprecharge active (3) h h x v h l h l l read active (3) h h x v l column address (a0 a9) l h l h read and autoprecharge active (3) h h x v h l h l h ( extended ) mode register set idle h h x v op code l l l l no - operation any h x x x x x l h h h device deselect any h x x x x x h x x x re fresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x l h h h power down mode entry idle h l x x x x h x x x l h h h power down mode exit any l h x x x x h x x x l h h h data in put mask disable active h x l x x x x x x x data input mask enable( 4) active h x h x x x x x x x note 1: v=valid data, x=don't care, l=low level, h=high level note 2: cken signal is input level when commands are provided. cken -1 signal is input level one clock cycle before the commands are provided. note 3: these are states of bank designated by b a signal. note 4: ldm and udm can be enable d respectively. AS4C64M16D2-25BAN confidential - 8/59 - rev.1.0 dec 2015 functional description read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits regist ered coincident with the active command are used to select the bank and row to be accessed (ba0 - ba 2 select the bank; a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column locati on for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. ! power-up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*v ddq and odt *1 at a low state (all other inputs may be undefined. ) the v dd voltage ramp time must be no greater than 200ms from when v dd ramps from 300mv to v dd m in; and during the v dd voltage ramp, |v dd -v ddq | Q 0.3 v - v dd , v ddl and v ddq are driven from a single power converter output, and - v tt is limited to 0.95 v max, and - v ref tracks v ddq /2. or - apply v dd before or at the same time as v ddl . - apply v ddl befo re or at the same time as v ddq . - apply v ddq before or at the same time as v tt & v ref . at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. f or the minimum of 200 s after stable power and clock ( ck, ck # ), then apply nop or deselect and take cke high . 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs ( 2) command, provide l ow ?to ba0 and ba2 , high ?to ba1.) 6. issue emrs ( 3) command. (to issue emrs ( 3) command, provide ? ow ?to ba2, ? igh ?to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command, provide "l ow " to a0, "h igh " to ba0 and "l ow " to ba1 and ba2 .) 8. issue a mode register set command for dll reset . (to issue dll reset command, provide "h igh " to a8 and "l ow " to ba0 - ba2 ) 9. issue precharge all command. 10. issue 2 or more auto - refresh commands. 11. issue a mode regis ter set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll. ) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment) .if ocd calibration is not used, emrs ocd default command (a9=a8= a7= high ) followed by emrs ocd c alibration mo de exit command (a9=a8=a7= low ) must be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. note 1: to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. AS4C64M16D2-25BAN confidential - 9/59 - rev.1.0 dec 2015 ! mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, wr, and various vendor specific options to make ddr2 sdram useful for various applications.the default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0 and ba1, while controlling the state of address pins a0 - a12. the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the mode register.the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state.the mode register is divided into various fields depending on functionality. - burst length field (a2 , a1, a0) this field specifies the data length of column access and selects the burst length. - addressing mode select field (a3) the addressing mode can be interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 4 and 8 . - cas latency field (a6 , a5, a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) Q cas latency x t ck - test mode field: a7; dll reset mode field: a8 these two bits must be programmed to "00" in normal operation. - (ba0 - ba 1) : bank addresses to define mrs select ion. table 5. mode register bitmap b a2 ba1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *2 0 0 pd wr dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type a2 a1 a0 bl 0 no 0 normal 0 sequential 0 1 0 4 1 yes 1 test 1 interleave 0 1 1 8 note 1: .for ddr2 - 800, wr min is determined by t ck (avg) max and wr max is determined by t ck (avg) min. wr [cycles] = ru {t wr [ns]/t ck (avg)[ns]}, where ru stands for round up. the mode register must be programmed to this value.this is also used with t rp to determine t dal . n ote 2: ba2 i s reserved for future use and must be set to 0 when programming the mr. a12 active power down exit time write recovery for autoprecharge *1 0 fast exit (use t xard ) a11 a10 a9 wr(cycles) a6 a5 a4 cas latency 1 slow exit (use t xards ) 0 0 0 reserved 0 0 0 reserved 0 0 1 2 0 0 1 reserved ba1 ba0 mrs mode 0 1 0 3 0 1 0 reserved 0 0 mr 0 1 1 4 0 1 1 3 0 1 emr(1) 1 0 0 5 1 0 0 4 1 0 emr(2) 1 0 1 6 1 0 1 5 1 1 emr(3) 1 1 0 reserved 1 1 0 6 1 1 1 reserved 1 1 1 reserved AS4C64M16D2-25BAN confidential - 10/59 - rev.1.0 dec 2015 ! extended mode register set (emrs) - emr(1) the extended mode register(1) stores the data for enabling or disabling the dll, output driver strength, odt value selection and additive late ncy. the default value of the extended mode register is not defined, therefore the extended mode register must be written after power - up for proper operation. the extended mode register is written by asserting low on cs # , ras # , cas # , we # , ba1 and high on b a0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register. mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data - output driver. a3~a5 determine the additive latency, a2 and a6 are used for odt value selection, a7~a9 are used for ocd control, a10 is used for dqs# disable . - dll enable/disable the dll must be enabled for normal o peration. dll enable is required during power up initialization , and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self refresh operation and is automatically re - enabled upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck pa rameters. table 6. extended mode register emr (1) bitmap b a2 ba1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *3 0 1 qoff 0 *3 dqs# ocd program rtt additive latency rtt d.i.c dll extended mode register ba1 ba0 mrs mode a6 a2 rtt (nominal) 0 0 mr 0 0 odt disable a0 dll enable 0 1 emr(1) 0 1 75 0 enable 1 0 emr(2) 1 0 150 1 disable 1 1 emr(3) 1 1 50 a9 a8 a7 ocd calibrati on program a1 output driver impedance control 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 reserved 0 full strength 0 1 0 reserved 1 reduced strength 1 0 0 reserved 1 1 1 ocd calibration default *1 a5 a4 a3 additive latency 0 0 0 0 a12 qoff *2 0 0 1 1 0 output buffer enabled 0 1 0 2 a10 dqs# 1 output buffer disabled 0 1 1 3 0 enable 1 0 0 4 1 disable 1 0 1 5 1 1 0 reserved 1 1 1 reserved note 1: after setting to default, ocd calibration mode needs to be exited by setting a9 - a7 to 000. note 2 : output disabled dqs, dqss, dqss#.this feature is intended to be used during i dd characterization of read current. n ote 3: a11 and ba2 are reserved for future use and must be set to 0 when programming the mr. AS4C64M16D2-25BAN confidential - 11/59 - rev.1.0 dec 2015 - emr(2) the extended mode register (2) controls refresh related features. the default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power - up for proper operation. the extended mode register(2) is written by asserting low on cs # , ras # , cas # , we #, high on ba1 and low on ba0, while controlling the st a tes of address pins a0 ~ a1 2 . the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register (2). the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register (2). mode register contents can be changed using the same command and clock c ycle requirements during normal operation as long as all banks are in the precharge state. table 7. extended mode register emr(2) bitmap b a2 ba1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *3 1 0 0 *1 srf 0 *1 extended m ode register(2) a7 high temperature self - refresh rate enable 0 disable 1 enable *2 note 1: the rest bits in emrs(2) are reserved for future use and all bits in emrs(2) except a7, ba0 and ba1 must be programmed to 0 when setting the extended mode register(2) during initialization. note 2: due to the migration natur e , user needs to ensure the dram part supports higher than 85 tcase temperature self - refresh entry. if the high temperature self - refresh mode is supported then controller can set the emrs2[a7] bit to enable the self - refresh rate in case of higher than 85 temperature self - refresh operation. n ote 3: ba2 is reserved for future use and must be set to 0 when programming the mr. AS4C64M16D2-25BAN confidential - 12/59 - rev.1.0 dec 2015 - emr(3) n o function is defined in extended mode register(3).the default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation. table 8. extended mode register emr (3) bitmap b a2 ba1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *1 1 1 0 *1 extended mode register(3) note 1: all bits in emr ( 3) except ba0 and ba1 are reserved for future use and must be set to 0 when programming the emr ( 3). AS4C64M16D2-25BAN confidential - 13/59 - rev.1.0 dec 2015 ! odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance for each dq, udqs/udqs # , ldqs/ldqs # , udm, and ldm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function is support ed for active and standby modes . it is turned off and not supported in self refresh mode. figure 4. functional representation of odt sw1 rval1 v ddq sw1 rval1 v ssq sw3 rval3 v ddq sw3 rval3 v ssq sw2 rval2 v ddq sw2 rval2 v ssq input pin dram input buffer switch (sw1, sw2, sw3) is enabled by odt pin. selection among sw1, sw2, and sw3 is determined by rtt (nominal) in emr. termination included on all dqs, dm, dqs, and dqs# pins table 9. odt dc electrical characteristics parameter/condition symbol min. nom. max. unit note rtt effective impedance value for emrs(a6, a2)=0,1; 75 rtt1(eff) 60 75 90 1 rtt effective impedance value for emrs(a6,a2)=1,0;150 rtt2(eff) 120 150 180 1 rtt effective impedance value for emrs(a6,a2)=1,1;50 rtt3(eff) 40 50 60 1 rtt mismatch tolerance between any pull - up/pull - down pair rtt(mis) -6 - 6 % 2 n ote 1: measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin seperately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. () () ? ih il ih il v ac v ac rtt(eff)= i(v (ac))-i(v (ac)) note 2: measurement defintion for rtt (mis): measure volta ge (vm) at test pin (midpoint) with no load . 1100% ?? ? ?? ?? ddq 2xvm rtt(mis)= v AS4C64M16D2-25BAN confidential - 14/59 - rev.1.0 dec 2015 ! bank activate command the bank activate command is issued by holding cas # and we # high with cs # and ras # low at the rising edge of the clock. the bank addresses ba0 - ba 2 are used to select the desired bank. the row addresses a0 through a12 are used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdra m can accept a read or write command (with or without auto - precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd min specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive latencies of 0, 1, 2, 3, and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined (t rc ). the minimum time int erval between bank active commands is t rrd in order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. there are two rules. one for restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follows: - 8 bank device sequential bank activation restriction : no more than 4 banks may be activated in a rolling t faw window. converting to clocks is done by dividing t faw [ns] by t ck [ns] or t ck [ns], depending on the speed bin, and rounding up to next integer value. as an example of the rolling window, if ru{ (t faw / t ck ) } or ru{ (t faw / t ck ) } is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. - 8 bank device precharge all allowance : t rp for a precharge all command for an 8 bank d evice will equal to t rp + 1 x t ck or t rp + 1 x t ck , depending on the speed bin, where t rp = ru{ t rp / t ck } and t rp is the value for a single bank precharge. ! read and write access modes after a bank has been activated, a r ead or w rite cycle can be execute d. this is accomplished by setting ras # high , cs # and cas # low at the clock s rising edge. we # must also be defined at this time to determine whether the access cycle is a r ead operation (we # high ) or a w rite operation (we # low ). the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial r ead or w rite operation on successive clock cycles. the boundary of the burst cycle is strictly restricted to specific segments of the page length. any system or applicatio n incorporating random access memory products should be properly designed, tested, and qualified to ensure proper use or access of such memory products. disproportionate, excessive, and/or repeated access to a particular address or addresses may result in reduction of product life. ! posted cas# posted cas # operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas# r ead or w rite command to be issued immediately after the ras bank activate command (or any time during the ras # - cas #- delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the c as latency (cl). therefore if a user chooses to issue a r/w command before the t rcd min, then al (greater than 0) must be written into the emr(1). the write latency (wl) is always defined as rl - 1 ( r ead l atency - 1) where r ead l atency is defined as the sum of additive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) ! burst mode operation burst mode operation is used to provi de a constant flow of data to memory locations ( w rite cycle), or from memory locations ( r ead cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. f or 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either se quential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst r ead or w rite operations are supported. interruption of a burst r ead or w rite operation is prohibited, when burst length = 4 is programmed. for burst interruption of a r ead or w rite burst when burst length = 8 is used, see the burst interruption section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. AS4C64M16D2-25BAN confidential - 15/59 - rev.1.0 dec 2015 table 10 . burst definition, addressing sequence of sequential and int erleave mode burst length start address sequential interleave a2 a1 a0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 ! burst read command the burst read command is initiated by having cs # and cas # low while holding ras # and we # high at the rising edge of t he clock. the address inputs determine the starting column address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the r ead l atency (rl). the data s trobe output (dq s) is driven low 1 clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data - out appears on the dq pin in phase with the dqs signal in a so urce synchronous manner. the rl is equal to an additive latency (al) plus cas l atency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the al is defined by the extended mode register set (1 ) (emrs ( 1)). ddr2 sdram pin timings are specified for eithe r single ended mode or differen tial mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin ti mings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs a nd its complement, dqs # . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 1 0 k resis tor to insure proper operation. ! burst write operation the burst write command is initiated by having cs # , cas # and we # low while holding ras # high at the rising edge of the clock. the address inputs determine the starting column address. writ e la tency (wl) is defined by a r ead latency (rl) minus one and is equal to (al + cl - 1);and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe sig nal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for each positiv e dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, wh ich is 4 or 8 bit burst. when t he burst has finished, any additional data supp lied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time fr om the completion of the burst w rite to bank precharge is the w rite recovery time (wr). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at the specified ac/dc levels. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs # . t his distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 10k resistor to insure prop er operation. AS4C64M16D2-25BAN confidential - 16/59 - rev.1.0 dec 2015 ! write data mask one w rite data mask (dm) pin for each 8 data bits (dq) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on w rite operations as the data bits, and though used in a uni - directional manner, is internally loaded identically to data bits to insure mat ched system timing. dm is not used during read cycles. ! precharge operation the precharge c ommand is used to precharge or close a bank that has been activated. the precharge command is triggered when cs # , ras # and we # are low and cas # is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba2, ba1, and ba0 are us ed to define which bank to precharge when the command is issued. table 11 . bank selection for precharge by address bits a10 ba2 ba1 ba0 precharged bank(s) low low low low bank 0 only low low low high bank 1 only low low high low bank 2 only low low hig h high bank 3 only low high low low bank 4 only low high low high bank 5 only low high high low bank 6 only low high high high bank 7 only high don t care don t care don t care all banks ! burst read operation followed by precharge minimum read to pre charge command spacing to the same bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which additive latency (al) + bl/2 clocks after a read command. a new bank active (command) may be issued to the same bank after the ras# precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initi ates the last 4 - bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time from al + 2 clocks aft er the read to the precharge command. ! burst write operation followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter and is not the programmed value for t wr in the mrs. AS4C64M16D2-25BAN confidential - 17/59 - rev.1.0 dec 2015 ! auto precharge operation before a new row in an active bank can be opened, the active bank must be precharged u sing either the precharge command or the auto - precharge function. when a read or a write command is given to the ddr2 sdram, the cas # timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the ear liest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high wh en the read or write command is issued, then the auto - precharge function is engaged. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto - precharge also be implemented during write commands. the precharge operation engaged by the auto precharge command will not begin until the last data of the burst write sequence is properly stored in the m emory array. this feature allows the precharge operation to be partially or completely hidden during burst r ead cycles (dependent upon cas latency) thus improving system performance for random data access. the ras # lockout circuit internally delays the pre charge operation until the array restore operation has been completed (t ras satisfied) so that the auto precharge command may be issued with any r ead or w rite command. ! burst read with auto precharge if a10 is high when a read command is issued, the read with auto - precharge function is engaged. the ddr2 sdram starts an auto - precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, th e start point of auto - precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of auto - precharge operation will be delayed until t rtp (min) is satisfied. in case the internal precharge is p ushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto - precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto - precharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks a fter the last 4 - bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras # precharge time (t rp ) has been satisfied from the clock at which the auto - precharge begins. (2) the ras # cycle time (t rc ) from the previous bank activation has been satisfied. ! burst write with auto precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins prech arge operation after the completion of the burst write plus w rite recovery time ( t wr ). the bank undergoing auto - precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) the data - in to bank activ ate delay time (wr + t rp ) has been satisfied. (2) the ras # cycle time (t rc ) from the previous bank activation has been satisfied. AS4C64M16D2-25BAN confidential - 18/59 - rev.1.0 dec 2015 table 1 2. precharge & auto precharge clariification from command to command minimum delay between from command to to comma nd unit note read precharge (to same bank as read) al+bl/2+max(rtp,2) -2 t ck 1,2 precharge all al+bl/2+max(rtp,2) -2 read w/ap precharge (to same bank as read w/ap) al+bl/2+max(rtp,2) -2 t ck 1,2 precharge all al+bl/2+max(rtp,2) -2 write precharge ( to same bank as write) wl+bl/2+ t wr t ck 2 precharge all wl+bl/2+ t wr write w/ap precharge (to same bank as write w/ap) wl+bl/2+ t wr t ck 2 precharge all wl+bl/2+ t wr precharge precharge (to same bank as precharge) 1 t ck 2 precharge all 1 precharg e all precharge 1 t ck 2 precharge all 1 n ote 1: rtp [ cycles ] =ru {t rtp [ ns]/ t ck ( avg ) [ ns]}, where ru stands for round up. note 2: for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank.the prechrage period is satisfied after t rp or t rp all( =t rp for 8 bank device + 1x t ck ) depending on the latest precharge command issued to that bank. ! refresh command when cs # , ras # and cas # are held low and we # high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the refresh command (ref) can be applied. an address counter, internal to the de vice, supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the ddr2 sdram will be in the precharged (idle) state. a delay between the refresh command (ref) and the next activate command or subsequent refresh command must be greater than or equal to the refresh cycle time (t rfc ).to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the abs olute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 * t refi . ! self refresh operation the sel f refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is defined by having cs # , ras # , cas # and cke # held low with we # high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs c ommand. once the command is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode all of the external signals except cke, are ?on t care? for proper self refresh operation all power supply pins (v dd , v ddq , v ddl and v ref ) must be at valid levels. the dram initiates a minimum of one refresh command internally within t cke pe riod once it enters self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self refresh entry is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock mu st be stable prior to cke going back high. once self refresh exit is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the enti re self refresh exit period t xsrd for proper operation except for self refresh re - entry. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command(refresh period o f t rfc ). nop or d eselect commands must be registered on each positive clock edge during the self refresh exit interval t xsnr . odt should be turned off during t xsrd . the use of self refresh mode introduces the possibility that an internally timed refresh ev ent can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. AS4C64M16D2-25BAN confidential - 19/59 - rev.1.0 dec 2015 ! p ower-down power - down is synchronously ente red when cke is registered low along with nop or deselect command. no read or write operation may be in progress when cke goes low . these operations are any of the following: read burst or write burst and recovery. cke is allowed to go low while any of oth er operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exit ing power - down mode for proper read operation. if power - down occurs when all banks are precharged, this mode is referred to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. for active power - down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low ?this mode is referred as ?tandard active power - down mode and a fast power - dow n ex it timing defined by the t xard tim ing parameter can be used. when a12 is set to high ?this mode is referred as a power saving low power active power - down mode . this mode takes longer to exit from the power - dow n mo de and the t xards timing parameter has to be satisfied. entering power - down deactivates the input and out put buffers, excluding ck, ck # , odt and cke. also the dll is disabled upon entering precharge power - down or slow exit active power - down, but the dll is kept enabled during fast exit active power - down. in power - down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are don t care . power - down duration is limited by 9 times t refi of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be applied with power - down exit latency, t xp , t xard or t xards , after cke goes high . power - down exit latencies are defined in the ac spec table of this data sheet. ! asynchronous cke low event dram requires cke to be maintained high for all valid operations as defined in this datasheet. if cke asynchronously drops low during any valid peration dram is not guaranteed to preserve the contents of array. if this event occurs, memo ry controller must satisfy dram timing specification tdelay efore turning off t he cl ocks. stable clocks must exist at the input of dram before cke is raised high again. dram must be fully re - initialized. dram is ready for normal operation after the initi alization sequence. ! input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. depen ding on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc. during dll re - lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ! no operation command the no operation command should be used in cases when the ddr2 sdram is in an idle or a wait state. the purpose of the no operation command (nop) is to prevent the ddr2 sdram from registering any unwanted commands between operations. a no operation command is registered when cs # is low with ras # , cas # , and we # held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. ! deselect command the des elect command performs the same function as a no operation command. deselect command occurs when cs # is brought high at the rising edge of the clock, the ras # , cas # , and we # signals become don t cares. AS4C64M16D2-25BAN confidential - 20/59 - rev.1.0 dec 2015 table 1 3. absolute maximum dc ratings symbol para meter value unit note v dd voltage on v dd pin relative to vss - 1.0 ~ 2.3 v 1,3 v ddq voltage on v ddq pin relative to vss - 0.5 ~ 2.3 v 1,3 v ddl voltage on v ddl pin relative to vss - 0.5 ~ 2.3 v 1,3 v in , v out voltage on any p in relative to vss - 0. 5 ~ 2.3 v 1,4 t stg storage t emperature - 55~1 00 c 1 ,2 n ote1 : stress greater than those listed under absolute maximum ratings may cause permanent damage to the devices. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note2: storage temperature is the case temper ature on the center/top side of the dram. note3: when v dd and v ddq and v ddl are less than 500mv, vref may be equal to or less than 300mv. note4 : voltage on any input or i/o may not exceed voltage on v ddq . t able 1 4. operating temperature condition symbol parameter value unit note t oper automotive t emperature -4 0~105 c 1 n ote 1: operating temperature is the case surface temperature on center/top of the dram. n ote2 : if tc exceeds 85 c , the dram must be refreshed externally at 2x refr esh. it is required to set trefi=3.9? in auto refresh mode and to set ??for emrs (2) bit a7 in self refresh mode. table 1 5. recommended dc operating conditions (sstl_1.8) symbol parameter min. typ. max. unit note v dd power s upply v oltage 1.7 1.8 1.9 v 1 v ddl power s upply v oltage f or dll 1.7 1.8 1.9 v 5 v ddq power s upply v oltage for i/o buffer 1.7 1.8 1.9 v 1,5 v ref input r eference v oltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq mv 2,3 v tt termination v oltage v ref - 0.04 v ref v ref + 0.04 v 4 note1 : th ere is no specific device vdd supply voltage requirement for sstl_18 compliance. however under all conditions v ddq must be less than or equal to v dd. note2 : the value of v ref may be selected by the user to provide optimum noise margin in the system. typica lly the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . note3 : peak to peak ac noise on v ref may not exceed +/ - 2 % v ref (dc). note4 : v tt of transmitting device must track v ref of receiving device. note5 : v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v ddl tied together AS4C64M16D2-25BAN confidential - 21/59 - rev.1.0 dec 2015 table 16. input logic level symbol parameter - 25 unit min. max. v ih (dc) dc input logic high voltage v ref + 0.125 v ddq + 0. 3 v v il (dc) dc input low voltage - 0.3 v ref - 0.125 v v ih ( ac ) ac input high voltage v ref + 0. 2 v ddq +v peak v v il ( ac ) ac input low voltage v ss q v peak v ref 0. 2 v v id (a c) ac different ial voltage 0.5 v ddq v v ix (a c) ac differential crosspoint voltage 0.5 x v ddq - 0.175 0.5 x v ddq +0.175 v n ote 1: refer to ove rshoot/undershoot specification for v peak value: maximum peak amplitude allowed for overshoot and undershoot . table 17. ac input test conditions symbol parameter value unit note v ref input reference voltage 0.5 x v ddq v 1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew rate input signal minimum slew rate 1.0 v /ns 2, 3 note1 : input waveform timing is referenced to the input signal crossing through the v ih / il ( ac ) level applied to the device under test. note2 : the input signal minimum slew rate is to be maintained over the range from v ref to v ih ( ac ) min for rising edges and the range from v ref to v il ( ac ) max for falling edges . note3 : ac timings are referenced with input waveforms switching from v il ( ac ) to v ih ( ac ) on the positive transitions and v ih ( ac ) to v il ( ac ) on the negative transitions. table 18 . differential ac output parameters symbol parameter value unit note min. max. v ox(ac) ac differenti al cross point voltage 0.5x v ddq - 0.125 0.5x v ddq +0.125 v 1 note1 : the typical value of v ox ( ac ) is expected to be about 0.5 x v ddq of the transmitting device and v ox ( ac ) is expected to track variations in v ddq . v ox ( ac ) indicates the voltage at which diffe rential output signals must cross. table 1 9. ac overshoot/undershoot specification for address and control pins (a0- a12, ba0 -ba 2, cs#, ras#, cas#, we#, cke, odt) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak am plitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.66 v- ns maximum undershoot area below v ss 0.66 v- ns AS4C64M16D2-25BAN confidential - 22/59 - rev.1.0 dec 2015 table 20. ac overshoot/undershoot specification for clock, data, strobe, and mask pins (dq, udqs, ldqs, udqs#, ldqs#, dm, ck, ck#) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.23 v- ns maximum undershoot area below v ss 0.23 v- ns table 21. output ac test conditions symbol parameter value unit note v otr output timing measurement reference level 0.5xv ddq v 1 note1 : the v ddq of the device under test is referenced. table 2 2. output dc current drive symbol parameter sstl_18 unit note i oh (dc) outp ut minimum source dc current - 13.4 ma 1, 3, 4 i ol (dc) output minimum sink dc current 13.4 ma 2, 3, 4 note1 : v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq ) /i oh must be less than 21 for values of v out between v ddq and v ddq - 280 mv. note2 : v ddq = 1.7 v; v o ut = 280 mv. v out /i ol must be less than 21 for values of v out between 0 v and 280 mv. note3 : the dc value of v ref applied to the receiving device is set to v tt note4 : the values of i oh ( dc ) and i ol ( dc ) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and vil max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see je dec standard : section 3.3 of jesd8 - 15a) along a 21 load line to define a convenient driver current for measurement. table 2 3. capacitance (v dd = 1.8 v, f = 1mhz, t op er = 25 c) symbol parameter d dr2 - 800 unit min. max. c in input capacitance : command and address 1 .0 1.75 pf c ck input capacitance (c k, ck#) 1 .0 2.0 pf c i/o dm, dq, dqs input/output capacitance 2 .5 3.5 pf dc in delta input capacitance: command and address - 0.25 pf dc ck delta input capacitance: ck, ck# - 0.25 pf dc io delta input/output capacitance: dm, dq, dqs - 0.5 pf n ote : these p arameters are periodically sampled and are not 100% tested. AS4C64M16D2-25BAN confidential - 23/59 - rev.1.0 dec 2015 table 24. idd specification parameters and test conditions (v dd = 1.8 v 0.1 v, t oper = -4 0~105 c) parameter & test condition symbol - 25 unit max. operating one bank active - precharge current: t ck =t ck ( min ), t rc = t rc ( min ), t ras = t ras ( min ); cke is high, cs # is high between valid commands; address bus inputs are switching ; data bus inputs are switching i dd0 72 ma operating one bank active - read - precharge current: i out = 0ma; bl = 4 , cl = cl ( min ) , al = 0; t ck = t ck ( min ) ,t rc = t rc ( min ) , t ras = t ras ( min ) , t rcd = t rcd ( min ) ;cke is high, cs # is high between valid commands;address bus inputs are switching; data pattern is same as i dd4w i dd1 90 ma precharge power - down current: all ban ks idle;t ck =t ck ( min ) ; cke is low; other control and address bus inputs are stable ; data bus inputs are floating i dd2p 11 ma precharge quiet standby current: all banks idle; t ck =t ck ( min ) ; cke is high, cs # is high; other control and address bus inputs are stable ; data bus inputs are floating i dd2q 22 ma precharge standby current: all banks idle; t ck = t ck ( min ) ; cke is high, cs # is high; other control and address bus inputs are switching ; data bus inputs are switching i dd2n 30 ma active power - down cu rrent: all banks open; t ck =t ck ( min ) ; cke is low; other control and address bus inputs are stable ; data bus inputs are floating mrs(a12)=0 i dd3p 28 ma mrs(a12)=1 20 ma active standby current: all banks open; t ck = t ck ( min ) , t ras = t ras ( max ) , t rp = t rp ( min ) ; cke is high, cs# is high between valid commands; other control and address bus inputs are switching ; data bus inputs are switching i dd3n 39 ma operating burst write current: all banks open,continuous burst writes; bl = 4, cl = cl ( min ) , al = 0; t ck = t ck ( min ) , t ras = t ras ( max ) , t rp = t rp ( min ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 156 ma operating burst read current: all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl ( min ) , al = 0; t ck = t ck ( min ) , t ras = t ras ( max ) , t rp = t rp ( min ) ; cke is high, cs # is high between valid commands; address bus inputs are switching ; data bus inputs are switching i dd4r 138 ma burst refresh current: t ck = t ck ( mi n) ; refresh command at every t rfc ( min ) interval; cke is high, cs # is high between valid commands; other control and address bus inputs are switching ; data bus inputs are switching i dd5 120 ma self refresh current: ck and ck # at 0v; cke 0.2v;other cont rol and address bus inputs are floating ; data bus inputs are floating i dd6 18 ma operating bank interleave read current: all bank interleaving reads, i out = 0ma; bl = 4, cl = cl ( min ) , al =t rcd ( min ) - 1 x t ck ( min ) ; t ck = t ck ( min ) , t rc = t rc ( min ) , t rrd = t rrd ( min ) , t rcd = t rcd ( min ) ; cke is high, cs# is high between valid commands; address bus inputs are stable during deselect s .data pattern is same as idd4r i dd7 240 ma AS4C64M16D2-25BAN confidential - 24/59 - rev.1.0 dec 2015 table 2 5. electrical characteristics and recommended a.c. operating conditions (v dd = 1.8v 0.1v , t op er = -4 0~105 c) symbol parameter - 25 unit specific notes min. max. t ck(avg) average clock period cl=4 3.75 8 ns 1 5, 33, 34 cl=5 2.5 8 ns 1 5, 33, 34 cl= 6 2.5 8 ns 1 5, 33, 34 cl= 7 - - ns 1 5, 33, 34 t ch(avg) average clock high pulse width 0.4 8 0.52 t ck 34, 35 t cl(avg) average clock low pulse width 0.4 8 0.52 t ck 34, 35 wl write command to dqs associated clock edge rl -1 t ck t dqss dqs latching rising transitions to associated clock edges - 0.25 0.25 t ck 28 t dss dqs fallin g edge to ck setup time 0.2 - t ck 28 t dsh dqs falling edge hold time from ck 0.2 - t ck t dqsh dqs input high pulse width 0.35 - t ck t dqsl dqs input low pulse width 0.35 - t ck t wpre write preamble 0.35 - t ck t wpst write postamble 0.4 0.6 t ck 10 t is(base) address and control input setup time 0.175 - ns 5, 7, 9, 2 2, 27 t ih(base) address and control input hold time 0.25 - ns 5, 7, 9, 2 3, 27 t ipw control & address input pulse width for each input 0.6 - t ck t ds(base) dq & dm input setup time 0.05 - ns 6-8 , 20, 2 6, 29 t dh(base) dq & dm input hold time 0.125 - ns 6-8 , 21 , 2 6, 29 t dipw dq and dm input pulse width for each input 0.35 - t ck t ac dq output access time from ck, ck# - 0.4 0.4 ns 38 t dqsck dqs output access time from ck, ck# - 0.35 0.35 ns 38 t hz data - out high - impedance time from ck, ck# - t ac (max) ns 1 8, 38 t lz(dqs) dqs(dqs#) low - impedance time from ck, ck# t ac (min) t ac (max) ns 1 8, 38 t lz(dq) dq low - impedance time from ck, ck# 2t ac (min) t ac (max) ns 1 8, 38 t dqsq dqs- dq skew for dqs and a ssociated dq signals - 0.2 ns 13 t hp ck half pulse width min (t ch ,t cl ) - ns 11, 12, 35 t qhs dq hold skew factor - 0.3 ns 12, 36 t qh dq/dqs output hold time from dqs t hp -t qhs - ns 37 t rpre read preamble 0.9 1.1 t ck 19, 39 t rpst read postamble 0.4 0.6 t ck 19, 40 t rrd active to active command period 10 - ns 4, 30 t faw four activate window 45 - ns 4, 30 t ccd cas# to cas# command delay 2 - t ck t wr write recovery time 15 - ns 30 t dal auto power write recovery + precharge time wr + t rp - ns 14, 31 t wtr internal write to read command delay 7.5 - ns 3, 24, 30 t rtp internal read to precharge command delay 7.5 - ns 3, 30 t cke cke minimum pulse width 3 - t ck 25 t xs nr exit self refresh to non - read command delay t rfc +10 - ns 30 t xs rd exit self refresh to a read command 200 - t ck t xp exit precharge power down to any command 2 - t ck t xard exit active power down to read command 2 - t ck 1 t xards exit active power down to read command(slow exit, lower power) 8- al - t ck 1, 2 AS4C64M16D2-25BAN confidential - 25/59 - rev.1.0 dec 2015 t aond odt turn - on delay 2 2 t ck 16 t aon odt turn - on t ac(min) t ac(max) +0.7 ns 6, 16, 38 t aonpd odt turn - on (power - down mode) t ac(min) +2 2 t ck +t ac(max) +1 ns t aofd odt turn - off delay 2.5 2.5 t ck 17, 42 t aof odt turn - off t ac(min) t ac(max) +0.6 ns 17, 41, 42 t aofpd odt turn - off ( power - down mode) t ac(min) +2 2.5 t ck +t ac(max) +1 ns t anpd odt to power down entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck t mrd mode register set command cycle time 2 - t ck t mod mrs command to odt update delay 0 12 ns 30 t delay mi nimum time clocks remains on after cke asynchronously drops low t is + t ck +t ih - ns 15 t rfc refresh to active/refresh command time 127.5 - ns 43 t refi average periodic refesh interval @ -40 c to +85 c 7.8 s 43 @ +85 c to 105 c 3.9 s 43 t rcd ras# to cas# delay time 12.5 - ns t rp row precharge delay time 12.5 - ns t rc row cycle delay time 57.5 - ns t ras row active delay time 45 70k ns AS4C64M16D2-25BAN confidential - 26/59 - rev.1.0 dec 2015 general notes, which may apply for all ac parameters: note 1: ddr2 sdram ac timing reference load the below figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. figure 5. ac timing reference load vddq dut dqs dqs# dq v tt =v ddq /2 25 ? timing reference point ouput the output timing reference voltage level for single ended signals i s the crosspoint with vtt. the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs # ) signal . note 2: slew rate measurement levels a) output slew rate for falling and rising edges is measured between v tt - 250 mv and v tt + 250 mv for single ended signals. for differential signals (e.g. dqs dqs # ) output slew rate is measured between dqs dqs # = - 500 mv and dqs dqs # = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from v ref ( dc) to v ih ( ac) , min for rising edges and from v ref (dc) to v il (ac),max for falling edges.for d ifferential signals (e.g. ck ck # ) slew rate for ris ing edges is measured f rom ck ck # = - 250 mv to ck - ck # = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) v id is the magnitude of the difference between the input voltage on ck and the input voltage on ck # , or betweendqs and dqs # for differential strobe. note 3: ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as bellow figure 6. slew rate test load vddq dut dqs dqs# dq v tt =v ddq /2 25 ? test point ouput AS4C64M16D2-25BAN confidential - 27/59 - rev.1.0 dec 2015 note 4: differential data strobe ddr2 sdram pin timings are specified for eithe r single ended mode or differential mode depending on the s etting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs # . this distinction i n timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs # , must be tied externally to v ss through a 20 to 10 k resistor to insure proper operation note 5: ac timings are for linear signal transitions. note 6: all voltages are referenced to v ss . note 7: these parameters guarantee device behavior, but they are not necessarily tested on each device.they may be guaranteed by devic e design or tester correlation note 8: tests for ac timing, i dd , and electrical (ac and dc) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage rang e specified. specific notes for dedicated ac parameters note 1: user can choose which active power down exit timing to use via mrs (bit 12). t xard is expected to be used for fast active power down exit timing. t xards is expected to be used for slow active power do wn exit timing where a lower power value is defined by each vendor data sheet. note 2: al=additive latency. note 3: this is a minimum requirement. minimum read to precharge timing is al+bl/2 provided that the t rtp and t ras (min) have been satisfied. note 4: a minimum of two clo cks (2* t ck ) is required irrespective of operating frequency. note 5: timings are specified with command/address input slew rate of 1.0 v/ns. note 6: timings are specified with dqs, dm, and dqs s ( in single ended mode) input slew rate of 1. 0v/ns. note 7: timings are specified w ith ck/ck # differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode . note 8: data setup and hold time derating. for all inpu t signals the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet . t ds(base) and t dh(base) value to the t ds and t dh derating value respectively. example: t ds (total setup time) =t ds (base) + t ds .for slew rates in between the values listed in tables 26 , the derating values may obtained by linear interpolation.these values are typically not subject to production test. they are verified by design and characterization. table 26. ddr2 -800 tds/tdh derating with differential data strobe tds, t dh derating values for dd2- 800 (all units in ps ; the note applies to the entire table) dqs,dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h dq slew rate v/ns 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 - 14 -5 - 14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - - 13 - 31 -1 - 19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - - 10 - 42 2 - 30 14 - 18 26 -6 38 6 - - 0.6 - - - - - - - - - 10 - 59 2 - 47 14 - 35 26 - 23 38 - 11 0.5 - - - - - - - - - - - 24 - 89 - 12 - 77 0 - 65 12 - 53 0.4 - - - - - - - - - - - - - 52 - 140 - 40 - 128 - 28 - 116 AS4C64M16D2-25BAN confidential - 28/59 - rev.1.0 dec 2015 note 9: t is and t ih (input setup and hold) derating for all input signals the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is(base) and t ih(base) value to the t is and tih derating value respectively. example: t is (total setup time) = t is (base) + t is for slew rates in between the values listed in t ables 27 , the derating values may obtained by linear interpolation.these values are typically not subject to production test. they are verified by design and characterization table 27. derating values for ddr2-800 tis and tih derating values for dr2 - 800 ck,c k# differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns tis tih tis tih tis tih units notes command/ address slew rate (v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 - 14 +25 +16 +55 +46 ps 1 0.8 - 13 - 31 +17 -1 +47 +29 ps 1 0.7 - 22 - 54 +8 - 24 +38 +6 ps 1 0.6 - 34 - 83 -4 - 53 +26 - 23 ps 1 0.5 - 60 - 125 - 30 - 95 0 - 65 ps 1 0.4 - 100 - 188 - 70 - 158 - 40 - 128 ps 1 0.3 - 168 - 292 - 138 - 262 - 108 - 232 ps 1 0.25 - 200 - 375 - 170 - 345 - 140 - 315 ps 1 0.2 - 325 - 500 - 295 - 470 - 265 - 440 ps 1 0.15 - 517 - 708 - 487 - 678 - 457 - 648 ps 1 0.1 - 1000 - 1125 - 970 - 1095 - 940 - 1065 ps 1 note 10: th e maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. note 11: min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). note 12: t qh = t hp t qhs , where: t hp = minimum half clock perio d for any given cycle and is defined by clock high or clock low (t ch , t cl ). t qhs accounts for: 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on t he next transition, both of which are, separately, due to data pin skew and output pattern effects, and p - channel to n- channel variation of the output drivers. note 13: t dqsq : consists of data pin skew and output pattern effects, and p - channel to n - channel variatio n of the output drivers as well as output slew rate mismatch between dqs / dqs # and associated dq in any given cycle. note 14: t dal = wr + ru{ t rp [ns] / t ck [ns] }, where ru stands for round up.wr refers to the t wr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. note 15: the clock frequency is allowed to change during self refresh mode or precharge power - down mode. in case of clock frequency change during precharge power - down . note 16: odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2 - 800, t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. AS4C64M16D2-25BAN confidential - 29/59 - rev.1.0 dec 2015 note 17: odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the b us is in high impedance. both are measured from t aofd , which is interpreted differently per speed bin. for ddr2 - 800 , if t ck (avg) = 2.5 ns is assumed, t aofd is 1. 25 ns (= 0.5 x 2.5 ns) after the second trailing clock edge counting from the clock edge that r egistered a first odt low and by counting the actual input clock edges. note 18: t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is n o longer driving (t hz ), or begins driving (t lz ). note 19: t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). the actual voltage measurement points are not critical as long as the calculation is consistent. note 20: input waveform timing t ds with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs # signals must be monotonic between v il (dc)max and v ih (dc)min. note 21: input wavefo rm timing t dh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il (dc) level for a rising signal applied to the device under test. dqs, dqs # signals must be monotonic between v il (dc)max and v ih (dc)min. note 22: input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. note 23: input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test . note 24: t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. note 25: t cke min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 cl ocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 x t ck + t ih . note 26: if t ds or t dh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. note 27: these parameters are measured from a command/address signal (cke, cs # , ras # , cas # , we #, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck # ) crossing. the spec values are not affected by the amount of c lock jitter applied (i.e. t jit (per), t jit (cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. note 28: these parameters are mea sured f rom a data strobe signal (l dqs/ u dqs) crossing to its respective clock signal (ck/ck # ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as these are relative to the clock signal crossi ng. that is, these parameters should be met whether clock jitter is present or not. note 29: these parameters are measured from a data signal ((l/ u ) dm , (l/u ) dq0 , (l/u ) dq1 , etc. ) transition edge to its respec tive data strobe signal ( l dqs/ u dqs /ldqs#/udqs# ) crossin g. note 30: for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / t ck (avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. note 31: t dal [t ck ] = wr [ t ck ] + trp [ t ck ] = wr + ru {t rp [ps] / t ck (avg) [ps] }, where wr is the value programmed in the mode register set. note 32: new units, t ck (avg) is introduced in ddr2 - 800. unit t ck (avg) represents the actual t ck (avg) of the input clock under operation. note 33: input clock jitter spec parameter. th ese parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to ddr2 - 800 only. the jitter specified is a random jitter meeting a gaussian distribution. AS4C64M16D2-25BAN confidential - 30/59 - rev.1.0 dec 2015 table 28. input clock jitter spec parameter parameter symbol - 25 unit note min . max . clock period jitter t jit ( per) - 100 100 ps 33 clock period jitter during dll locking period t jit (per,lck) - 80 80 ps 33 cycle to cycle clock period jitter t jit (cc) - 200 200 ps 33 cycle to cycle clock period jitter during dll locking period t jit (cc,lck) - 160 160 ps 33 cumulative error across 2 cycles t err (2per) - 150 150 ps 33 cumulative error across 3 cycles t err (3per) - 175 175 ps 33 cumulative error across 4 cycles t err (4per) - 200 200 ps 33 cumulative error across 5 cycles t err (5per) - 200 200 ps 33 cumulative error across n cycles, n=6...10, inclusive t err (6 - 10per) - 300 300 ps 33 cumulative error across n cycles, n=11...50, inclusive t err (11 - 50per) - 450 450 ps 33 duty cycle jitter t j it (duty) - 100 100 ps 33 note 34: these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min andmax of spec values are to be used for calculations in the table below.) table 29 . absolute clock period average values parameter symbol min . max . unit absolute clock period t ck (abs) t ck (avg),min + t jit (per),min t ck (avg),max + t jit (per),max ps absolute clock high pulse width t ch (abs) t ch (avg),min * t ck (avg),min + t jit (duty),min t ch (avg),max * t ck (avg),max + t jit (duty),max ps absolute clock low pulse width t cl (abs) t cl (avg),min * t ck (avg),min + t jit (duty),min t cl (avg), max * t ck (avg),max + t jit (duty), max ps note 35: t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for tqh calculation is determin ed by the following equation; t hp = min ( t ch (abs), t cl (abs) ), where, t ch (abs) is the minimum of the actual instantaneous clock high time; t cl (abs) is the minimum of the actual instantaneous clock low time; note 36: t qhs accounts for: 1) the pulse duration d istortion of on - chip clock circuits, which represents how well the actual t hp at the input is transferred to the output; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p - channel to n - channel variation of the output drivers note 37: t qh = t hp t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half - pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} AS4C64M16D2-25BAN confidential - 31/59 - rev.1.0 dec 2015 note 38: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err (6 - 10per) of the input clock. (output deratings are relative to the sdram input clock.) note 39: when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relati ve to the sdram input clock.) note 40: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jit (duty) of the input clock. (output deratings are relative to the sdram input clock.) note 41: when the device is operated with i nput clock jitter, this parameter needs to be derated by { - t jit (duty),max - t err (6 - 10per),max } and { - t jit (duty),min - t err (6 - 10per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) note 42: for t aofd of ddr2 - 800, the 1 /2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t ck (avg). t aof ,min and t aof ,max should each be derated by the same amount as the actual amount of t ch (avg) offset present at the dram input with re spect to 0.5. note 43: if refresh timing is violated, data corruption may occur and the data must be re - writtern with valid data before a valid read can be executed. AS4C64M16D2-25BAN confidential - 32/59 - rev.1.0 dec 2015 timing waveforms figure 7. initialization sequence after power-up ck ck# t ch cke command t cl t is odt t is nop pre all emr s mrs pre all ref ref mrs emr s emr s any cmd 400ns t rp t mrd t mrd t rp t mrd follow ocd flowchart t oit min 200 cycle dll enable dll reset ocd default ocd cal.mod e exit note 1: to guarantee odt off, v ref must be valid and a low level must be applied to the odt pin. t rfc t rfc figure 8. odt update delay timing-tmod ck updating rtt t is emrs nop nop nop nop nop cmd t aofd t mod, max t mod, min old setting new setting odt note 1: to prevent any impedance glitch on the channel, the following conditions must be met: - t aofd must be met before issuing the emrs command. - odt must remain low for the entire duration of t mod window, until t mod , max is met. then the odt is ready for normal operation with the new setting, and the odt signal may be raised again to turned on the odt. note 2: emrs command directed to emr(1), which updates the information in emr(1)[a6,a2], i.e. rtt (nominal). note 3: "setting" in this diagram is the register and i/o setting, not what is measured from outside. ck# figure 9. odt update delay timing-t mod , as measured from outside ck# ck rtt t is emrs cmd t aofd t mod, max old setting new setting odt nop nop nop nop nop t aond note 1: emrs command directed to emr(1), which updates the information in emr(1)[a6,a2], i.e. rtt (nominal). note 2: "setting" in this diagram is measured from outside. AS4C64M16D2-25BAN confidential - 33/59 - rev.1.0 dec 2015 figure 1 0. odt timing for active standby mode ck# t0 internal term res. t is t is t aond ck t1 t2 t3 t4 t5 t6 cke odt v ih(ac) t is v il(ac) t aofd t aon,min t aon,max t aof,min t aof,max rtt figure 1 1. odt timing for power- down mode ck# t0 internal term res. t is ck t1 t2 t3 t4 t5 t6 cke odt v ih(ac) t is v il(ac) t aofpd,max t aonpd,min rtt t aofpd,min t aonpd,max AS4C64M16D2-25BAN confidential - 34/59 - rev.1.0 dec 2015 figure 1 2. odt timing mode switch at entering power- down mode ck# ck t is cke t aofd t aond odt t anpd t-5 t-4 t-3 t-2 t-1 t0 t1 t2 t3 t4 entering slow exit active power down mode or precharge power down mode. rtt internal term res. t is v il(ac) odt rtt internal term res. t is v il(ac) t aofpd max active & standby mode timings to be applied. power down mode timings to be applied. t is v ih(ac) rtt active & standby mode timings to be applied. t aonpd max t is v ih(ac) power down mode timings to be applied. rtt odt odt internal term res. internal term res. AS4C64M16D2-25BAN confidential - 35/59 - rev.1.0 dec 2015 figure 1 3.odt timing mode switch at exit power- down mode ck# ck t is cke t aofd t aond odt t axpd t0 t1 t4 t5 t6 t7 t8 t9 t10 t11 exiting from slow active power down mode or precharge power down mode. internal term res. t is v il(ac) odt internal term res. t is v il(ac) active & standby mode timings to be applied. power down mode timings to be applied. t is v ih(ac) active & standby mode timings to be applied. t aonpd max t is v ih(ac) power down mode timings to be applied. odt odt internal term res. internal term res. rtt t aofpd max v ih(ac) rtt rtt rtt figure 14. bank activate command cycle (t rcd =3, al=2 , t rp =3, t rrd =2, t ccd =2) ck# t0 t1 t2 t3 tn tn+1 tn+2 internal ras# - cas# delay (>=t rcd min ) cas# - cas# delay time (t ccd ) t rcd = 1 read begins tn+3 bank a row addr. bank a col. addr. bank b row addr. bank b col. addr bank a addr. bank b addr. bank a row addr. additive latency delay (al) bank a activate bank a post cas# read bank b activate bank b post cas# read bank a precharge bank b precharge bank a activate ras# - ras# delay time (>=t rrd ) bank active (>=t ras ) bank precharge time (>=t rp ) ras# cycle time (>=t rc ) address command ck AS4C64M16D2-25BAN confidential - 36/59 - rev.1.0 dec 2015 read followed by a write to the same bank ck# cmd al=2 -1 1 2 3 4 5 6 7 8 9 0 10 11 12 active a-bank read a-bank write a-bank cl=3 wl=rl-1=4 dout 0 dout 1 dout 2 dout 3 din 0 din 1 din 2 din 3 rl=al+cl=5 >=t rcd [ al=2 and cl=3, rl= (al+cl)=5, wl= (rl-1)=4, bl=4] dqs dq ck dqs# figure 1 6. posted cas# operation: al=0 read followed by a write to the same bank ck# cmd al=0 -1 1 2 3 4 5 6 7 8 9 0 10 11 12 active a-bank read a-bank write a-bank cl=3 wl=rl-1=2 dout 0 dout 1 dout 2 dout 3 din 0 din 1 din 2 din 3 rl=al+cl=3 >=t rcd [ al=0 and cl=3, rl= (al+cl)=3, wl= (rl-1)=2, bl=4] dqs dq ck dqs# figure 1 5. posted cas# operation: al=2 AS4C64M16D2-25BAN confidential - 37/59 - rev.1.0 dec 2015 figure 1 7. data output (read) timing ck# ck dq t dqsq max ck t ch t rpst t rpre dqs t cl dqs# dqs q q q t qh q t qh t dqsq max dqs# figure 18 . burst read operation: rl=5 (al=2, cl=3, bl=4) ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 posted cas# read a nop nop nop nop nop nop nop nop =< t dqsck dout a0 dout a1 dout a2 dout a3 al=2 cl=3 rl=5 dqs# AS4C64M16D2-25BAN confidential - 38/59 - rev.1.0 dec 2015 figure 19 . burst read operation: rl=3 (al=0, cl=3, bl=8) ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 read a nop nop nop nop nop nop nop nop dout a0 dout a1 dout a2 dout a3 cl=3 rl=3 dqs# =< t dqsck dout a4 dout a5 dout a6 dout a7 figure 20. burst read followed by burst write: rl=5 , wl = (rl-1) =4, bl=4 ck ck# dqs cmd dqs t0 t1 tn-1 tn tn+1 tn+2 tn+3 tn+4 tn+5 post cas# read a nop nop post cas# write a nop nop nop nop nop dout a 0 rl=5 dqs# t rtw (read to write turn around time) wl = rl-1 = 4 dout a 1 dout a 2 dout a 3 din a 0 din a 1 din a 2 din a 3 note : the minimum time from the burst read command to the burst write command is defined by a read-to-write- turn-around-time, which is 4 clocks in case of bl = 4 operation, 6 clocks in case of bl = 8 operation. AS4C64M16D2-25BAN confidential - 39/59 - rev.1.0 dec 2015 figure 2 1. seamless burst read operation: rl=5 , al=2, cl=3, bl=4 ck ck# dqs cmd dqs t0 t1 t2 t3 t4 t5 t6 t7 t8 post cas# read a nop post cas# read b nop nop nop nop nop nop dout a0 al=2 dqs# dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 cl=3 rl=5 note : the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl =8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated. figure 2 2. read burst interrupt timing: (cl=3, al=0, rl=3, bl=8) ck# ck cmd read a nop read b nop nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7 dqs dqs# dqs note 1: read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. note 2: read burst of 8 can only be interrupted by another read command. read burst interruption by write command or precharge command is prohibited. note 3: read burst interrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. note 4: read burst interruption is allowed to any bank inside dram. note 5: read burst with auto precharge enabled is not allowed to interrupt. note 6: read burst interruption is allowed by another read with auto precharge command. note 7: all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum read to precharge timing is al+bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). AS4C64M16D2-25BAN confidential - 40/59 - rev.1.0 dec 2015 figure 2 3. data input (write) timing dqs# dq dqs t dqsh t wpre dqs dm t dqsl t wpsl v il(ac) v ih(ac) d d v il(dc) v ih(dc) d d dmin dmin dqs# dmin v ih(ac) v il(ac) dmin v ih(dc) v il(dc) t ds t ds t dh t dh AS4C64M16D2-25BAN confidential - 41/59 - rev.1.0 dec 2015 figure 24. burst write operation: rl=5 (al=2 , cl=3), wl=4, bl=4 ck# ck t dqss cmd case 1: with t dqss (max) >=t wr t0 t1 t2 t3 t4 t5 t6 t7 tn posted cas# write a nop nop nop nop nop nop nop precharge t dss t dqss t dss completion of the burst write wl = rl-1 =4 dna 0 dna 1 dna 2 dna 3 dqs dqs# >=t wr wl = rl-1 =4 dna 0 dna 1 dna 2 dna 3 dqs dqs# t dqss t dsh t dqss t dsh case 2: with t dqss (min) dqs dqs figure 25. burst write operation: rl=3 (al=0 , cl=3), wl=2, bl=4 ck# ck <=t dqss cmd >=t wr t0 t1 t2 t3 t4 t5 tm tm+1 tn write a nop nop nop nop nop precharge nop bank a activate completion of the burst write wl = rl-1 =2 dna 0 dna 1 dna 2 dna 3 dqs dqs# dqs >=t rp AS4C64M16D2-25BAN confidential - 42/59 - rev.1.0 dec 2015 figure 26. burst write followed by burst read: rl=5 (al=2, cl=3, wl=4, t wtr =2, bl=4) ck# ck cke t0 t1 t4 t5 t6 t7 t8 t9 t2 t3 nop nop nop nop post cas# read a nop nop nop nop dqs al=2 dqs# wl = rl-1 = 4 dqs# dqs cl=3 rl=5 >=t wtr dna 0 dna 1 dna 2 dna 3 dout a 0 dq note : the minimum number of clock from the burst write command to the burst read command is [cl-1 + bl/2 + t wtr ]. this t wtr is not a write recovery time (t wr ) but the time required to transfer the 4 bit write data from the input buffer into sense amplifiers in the array. t wtr is defined in the timing parameter table of this standard. write to read = cl-1+bl/2+t wtr figure 27. seamless burst write operation rl=5, wl=4, bl=4 ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# write a nop post cas# write b nop nop nop nop nop nop dqs dqs# wl = rl-1 = 4 dqs# dqs dna 0 dna 1 dna 2 dna 3 dq dnb 0 dnb 1 dnb 2 dnb 3 note : the seamless burst write operation is supported by enabling a write command every other clock for bl= 4 operation, every four clocks for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated. AS4C64M16D2-25BAN confidential - 43/59 - rev.1.0 dec 2015 figure 28. write burst interrupt timing: (cl=3, al=0, rl=3, wl=2, bl=8) ck# ck cmd nop write a nop write b nop nop nop nop nop nop a0 a1 a2 a3 b0 b1 b2 b3 b4 b5 b6 b7 dqs dqs# dqs note 1: write burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. note 2: write burst of 8 can only be interrupted by another write command. write burst interruption by read command or precharge command is prohibited. note 3: write burst interrupt must occur exactly two clocks after previous write command. any other write burst interrupt timings are prohibited. note 4: write burst interruption is allowed to any bank inside dram. note 5: write burst with auto precharge enabled is not allowed to interrupt. note 6: write burst interruption is allowed by another write with auto precharge command. note 7: all command timings are referenced to burst length set in the mode register. they are not referenced to actual burst. for example, minimum write to precharge timing is wl + bl/2 + twr where twr starts with the rising clock after the uninterrupted burst end and not from the end of actual burst end. AS4C64M16D2-25BAN confidential - 44/59 - rev.1.0 dec 2015 figure 29. write data mask dq dqs dm dqs# t ds v ih(ac) v ih(dc) v il(ac) v il(dc) t dh t ds v ih(ac) v ih(dc) v il(ac) v il(dc) t dh ck# ck command dqs dqs# dq write t wr wl t dqss t dqss dm case 2: max t dqss dqs dqs# dq dm case 1: min t dqss data mask function, wl=3, al=0, bl=4 shown data mask timing AS4C64M16D2-25BAN confidential - 45/59 - rev.1.0 dec 2015 figure 30. burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop precharge nop nop nop bank a active nop dqs dqs# al+bl'/2 clks douta 0 douta 1 douta 2 douta 3 dq >=t rp al=1 cl=3 rl=4 >=t ras >=t rtp cl=3 figure 3 1. burst read operation followed by precharge : (rl=4, al=1, cl=3, bl=8, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop precharge a nop nop nop dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 1 first 4-bit prefetch >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 AS4C64M16D2-25BAN confidential - 46/59 - rev.1.0 dec 2015 figure 3 2. burst read operation followed by precharge: (rl=5, al=2, cl=3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop precharge a nop nop bank a activate nop dqs dqs# rl= 5 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 2 >=t ras >=t rp cl = 3 >=t rtp figure 3 3. burst read operation followed by precharge: (rl=6, al=2, cl=4, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop precharge a nop nop bank a activate nop dqs dqs# rl= 6 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 4 al = 2 >=t ras >=t rp cl = 4 >=t rtp AS4C64M16D2-25BAN confidential - 47/59 - rev.1.0 dec 2015 figure 3 4. burst read operation followed by precharge : (rl=4, al=0, cl=4, bl=8, t rtp >2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop precharge a nop nop bank a activate dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + 2 + max( t rtp , 2 t ck )* cl = 4 al = 0 first 4-bit prefetch >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 >=t rp >=t ras *: rounded to next integer. figure 3 5. burst write operation followed by precharge : wl = (rl-1) =3 ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# write a nop nop nop nop nop nop nop precharge a dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's >=t wr wl= 3 completion of the burst write AS4C64M16D2-25BAN confidential - 48/59 - rev.1.0 dec 2015 figure 3 6. burst write followed by precharge : wl = (rl-1) =4 ck# ck cmd t0 t1 t4 t5 t6 t7 t9 t2 t3 post cas# write a nop nop nop nop nop nop nop precharge a dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's >=t wr wl= 4 completion of the burst write figure 3 7. burst read operation with auto precharge: (rl=4,al=1, cl=3, bl=8, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop nop bank a activate dqs dqs# rl= 4 dout a 0 dout a 1 dout a 2 dout a 3 dq's al + bl/2 clks cl = 3 al = 1 autoprecharge >=t rtp second 4-bit prefetch dout a 4 dout a 5 dout a 6 dout a 7 >= t rp t rtp precharge begins here first 4-bit prefetch AS4C64M16D2-25BAN confidential - 49/59 - rev.1.0 dec 2015 figure 3 8. burst read operation with auto precharge: (rl=4, al=1, cl=3, bl=4, t rtp >2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop bank a activate nop dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 autoprecharge >= al+t rtp +t rp al= 1 rl= 4 t rtp t rp first 4-bit prefetch precharge begins here figure 3 9. burst read operation with auto precharge followed by activation to the same bank (t rc limit): rl=5(al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop nop bank a activate dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 >=t ras (min) al= 2 rl= 5 >= t rc cl=3 a10= 1 auto precharge begins >=t rp AS4C64M16D2-25BAN confidential - 50/59 - rev.1.0 dec 2015 figure 40. burst read operation with auto precharge followed by an activation to the same bank (t rp limit): (rl=5 (al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) ck# ck cmd t0 t1 t4 t5 t6 t7 t8 t2 t3 post cas# read a nop nop nop nop nop nop bank a activate nop dqs dqs# douta 0 douta 1 douta 2 douta 3 dq's cl= 3 >=t ras (min) al= 2 rl= 5 >= t rc cl=3 a10= 1 auto precharge begins >= t rp figure 41. burst write with auto-precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 ck# ck cmd t0 t1 t4 t5 t6 t7 tm t2 t3 post cas# wra bank a nop nop nop nop nop nop nop bank a active dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's auto precharge begins wl= rl-1=2 completion of the burst write a10 = 1 >=wr >=t rp >=t rc AS4C64M16D2-25BAN confidential - 51/59 - rev.1.0 dec 2015 figure 42. burst write with auto-precharge (wr+t rp ): wl=4, wr=2, bl=4, t rp =3 ck# ck cmd t0 t3 t6 t7 t8 t9 t12 t4 t5 post cas# wra bank a nop nop nop nop nop nop nop bank a active dqs dqs# dna 0 dna 1 dna 2 dna 3 dq's auto precharge begins wl= rl-1=4 completion of the burst write a10 = 1 >=wr >=t rp >=t rc figure 43. refresh command ck# ck cke t0 t1 tm tn tn+1 t2 t3 precharge nop nop ref ref nop any cmd high >=t rp >=t rfc >=t rfc AS4C64M16D2-25BAN confidential - 52/59 - rev.1.0 dec 2015 figure 44. self refresh operation ck# ck cke t0 t1 t5 tm t2 t3 cmd >=t xsnr t rp* t ch t cl t ck t4 t6 tn >=t xsrd t is v il(ac) v ih(ac) t is nop self refresh odt t aofd t is v il(ac) t ih t is t ih t is t ih v il(dc) v il(ac) v ih(ac) v ih(dc) nop nop valid note 1 device must be in the "all banks idle" state prior to entering self refresh mode. note 2 odt must be turned off t aofd before entering self refresh mode, and can be turned on again when t xsrd timing is satisfied. note 3 t xsrd is applied for read or a read with autoprecharge command. t xsnr is applied for any command except a read or a read with autoprecharge command. figure 45 . basic power down entry and exit timing diagram ck# ck command cke valid t ih t cke min t ih t ih t ih t is t is t is nop nop nop valid valid or nop t xp, t xard t xards t cke(min) exit power-down mode don't care enter power-down mode figure 46 . cke intensive environment ck# cke t cke note: dram guarantees all ac and dc timing & voltage specifications and proper dll operation with intensive cke operation ck t cke t cke t cke AS4C64M16D2-25BAN confidential - 53/59 - rev.1.0 dec 2015 figure 47 . cke intensive environment ck# cke t cke note: the pattern shown above can repeat over a long period of time. with this pattern, dram guarantees all ac and dc timing & voltage specifications and dll operation with temperature and voltage drift ck t cke t cke t cke t xp t xp t refi ref ref cmd figure 48. read to power-down entry ck# cmd bl=4 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl read operation starts with a read command and dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq ck# cmd bl=8 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq q q q q AS4C64M16D2-25BAN confidential - 54/59 - rev.1.0 dec 2015 figure 49. read with autoprecharge to power-down entry ck# cmd bl=4 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rda q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq ck# cmd bl=8 t0 t2 tx tx+1 tx+2 tx+3 tx+4 tx+5 tx+6 tx+7 t1 tx+8 tx+9 rd q al+cl dqs cke ck dqs# cke should be kept high until the end of burst operation t is q q q dq q q q q pre al+bl/2 with t rtp = 7.5ns & t ras min satisfied pre start internal precharge al+bl/2 with t rtp = 7.5ns & t ras min satisfied figure 50. write to power-down entry ck# cmd bl=4 t0 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 ty ty+1 t1 ty+2 ty+3 wr q wl dqs cke ck dqs# t is q q q dq ck# cmd bl=8 t0 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 t1 tx+3 tx+4 wr q wl dqs cke ck dqs# q q q dq q q q q t wtr t is t wtr AS4C64M16D2-25BAN confidential - 55/59 - rev.1.0 dec 2015 figure 51. write with autoprecharge to power-down entry ck# cmd bl=4 t0 tm tm+1 tm+2 tm+3 tx tx+1 tx+2 tx+3 tx+4 t1 tx+5 tx+6 wra q wl dqs cke ck dqs# t is q q q dq ck# cmd bl=8 t0 tm tm+1 tm+2 tm+3 tm+4 tm+5 tx tx+1 tx+2 t1 tx+3 tx+4 wra q wl dqs cke ck dqs# q q q dq q q q q wr*1 t is pre wr*1 pre start internal precharge *1: wr is programmed through mrs figure 52. refresh command to power -down entry ck# cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 ref cke ck t is t11 cke can go to low one clock after an auto-refresh command figure 53. active command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 act cke t is t11 cke can go to low one clock after an active command AS4C64M16D2-25BAN confidential - 56/59 - rev.1.0 dec 2015 figure 54. precharge/precharge -all command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 pr or pra cke t is t11 cke can go to low one clock after a precharge or precharge all command figure 55. mrs /emrs command to power-down entry cmd t0 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 mrs or emrs cke t is t11 t mrd figure 56. asynchronous cke low event ck# ck cke t ck t delay cke asynchronously drops low clocks can be turned off after this point t is stable clocks figure 57. clock frequency change in precharge power down mode ck# cmd t0 t2 t4 tx tx+1 ty ty+1 ty+2 ty+3 ty+4 t1 tz frequency change occurs here t rp cke odt ck nop nop nop nop dll reset nop valid 200 clocks t aofd minimum 2 clocks required before changing frequency stable new clock before power down exit t xp t is t is t ih odt is off during dll reset AS4C64M16D2-25BAN confidential - 57/59 - rev.1.0 dec 2015 figure 58. 84 -ball fbga package outline drawing information top view bottom view side view pin a1 index detail : "a" symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.010 -- 0.016 0.25 -- 0.40 a2 0.028 -- 0.031 0.70 -- 0.80 a3 -- -- 0.008 -- -- 0.20 d 0.311 0.315 0.319 7.9 8.0 8.1 e 0.488 0.492 0.496 12.4 12.5 12.6 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.441 -- -- 11.2 -- f -- 0.126 -- -- 3.2 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 d2 -- -- 0.081 -- -- 2.05 AS4C64M16D2-25BAN confidential - 58/59 - rev.1.0 dec 2015 part numbering system as4c 64m16d2 25 b a n dram 64m16=64mx16 d2=ddr2 25=400mhz b = fbga a=automotive (-40 c ~+105 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-6 10-6800 fax : 650-620-9211 www.alliancememory.com copyright ?alliance memory all rights reserved ?copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in l ife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS4C64M16D2-25BAN confidential - 59/59 - rev.1.0 dec 2015 |
Price & Availability of AS4C64M16D2-25BAN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |